From Analog Ct, Pt To Digital Process Bus - Hardware-In-The-Loop Protection Studies For Inverter-Dominated Transmission Systems

The global pursuit of decarbonization requires a significant increase in the integration of distributed energy resources (DERs), such as wind turbines and photovoltaic power plants. This transition is reshaping the grid into an inverter-dominated power system. However, inverter-based resources (IBRs) inherently provide limited fault current and may distort voltage waveforms during fault conditions. These characteristics, combined with increased system dynamics, call for new approaches to protection, as conventional schemes may no longer be effective. This paper is a continuation of our work presented last year, where a hardware test bed was introduced and initial results were discussed. Building on that foundation, we now include additional results from the hardware test bed, further validating protection performance in inverter-dominated scenarios. A new series of tests is being carried out in a hardware-in-the-loop (HIL) environment using the OPAL-RT real-time simulation platform. In this setup, process bus communication is employed, and sampled measured values (SMVs) are supplied to protection relays to evaluate their behavior under various system conditions. Compared with analog current and potential transformer interfaces, SMV-based testing more faithfully mirrors modern digital substations while eliminating scaling and wiring limitations. It also enables fault studies with reclosing sequences in the HIL environment, tests that are otherwise prohibitively complex or expensive to execute in pure hardware setups. The work is conducted within the U.S. Department of Energy funded project Protection-Inverter Co-Design for 100% Renewable Power Systems (PICO), which includes an application for Hawaiian Electric involving the transmission network of the Big Island grid. The study examines whether traditional protection methods - differential protection and Permissive Over-Reaching Transfer Trip (POTT) - remain viable at 100% IBR penetration, while also exploring advanced configurations combining line differential, POTT, distance, and overcurrent protection. The paper presents system configuration, results from the hardware test bed and HIL process bus testing, waveform analysis, and key lessons learned.